The present invention relates generally to computer systems, and more specifically, to vector memory access instructions for big-endian (BE) element ordered and little-endian (LE) element ordered computer code and data.
A computer system may implement a big-endian (BE) or a little-endian (LE) architecture. In a BE system, the most significant byte of an element in storage is stored in the smallest address in the element's memory location, and the least significant byte is stored in the largest address. In a LE system, the least significant byte of the element is stored in the smallest address in the element's memory location, and the most significant byte is stored in the largest address. For example, Intel™ systems are LE systems, while IBM z/Achitecture™ systems are BE systems. Complexity is introduced with the emergence of vector processing where a single vector storage access involves a plurality of values. BE systems have traditionally implemented vector comprised of a plurality of elements that are numbered 0 to N−1 from the leftmost element to the rightmost element, LE systems have traditionally implemented vector comprised of a plurality of elements that are numbered 0 to N−1 from the rightmost element to the leftmost element. The ordering of elements in a vector becomes an issue for certain vector operations that reference an element of the vector. BE systems will typically implement these instructions to reference the element as an index from the leftmost element, while LE systems will typically implement these instructions to reference the element as an index from the rightmost element.